1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device with impedance calibration function that means to calibrate internal load impedance in a semiconductor device to be compatible with impedance of an external cable when resistance in the semiconductor device varies due to parameter changes of semiconductor device fabrication process.
2. Description of Related Art
Recently, a serial data transmission system is getting adopted as a data transmission method to overcome limit of data transmission rate of a conventional parallel data transmission system. Generally, a serial data transmission system adopts a differential signal structure to increase noise immunity and uses a low voltage level signal to increase data transmission rate. Therefore, a Low Voltage Differential Signal (LVDS) system is successfully introduced into a market and a Serial Data Interface (SDI) such as Serial-ATA is being adopted in several applications.
In such serial data interface, impedance calibration between a transmitter and a receiver is very important. If impedance matching between a transmitter and a receiver is not properly performed, levels of transmission and receiving signals are changed. Further, the transmission and receiving signals are distorted due to reflected waves and Bit Error Rate (BER) of data transmission increases.
A specification of Serial-ATA which is a sort of serial data transmission system says that output impedance of a transmission driving circuit is differentially 100 xcexa9 (allowable error: 150 xcexa9), and impedance of a cable connected to the transmission driving circuit is 50 xcexa9 (differentially 100 xcexa9). Load resistance of the transmission driving circuit that determines output impedance of the transmission driving circuit is designed using resistance of a polysilicon layer or resistance of diffusion layer integrated in a semiconductor device. However, such resistance of a polysilicon layer or a diffusion layer in a semiconductor device generally have dispersion caused by process parameters, so that additional resistance adjusting means for satisfying the specification is needed.
It is a feature of an embodiment of the present invention to provide a semiconductor device capable of calibrating internal load impedance of a semiconductor device to be compatible with impedance of an external cable when real internal resistance value in a semiconductor device is different from a predetermined resistance value due to the change of process parameter in the fabrication of a semiconductor device.
In accordance with the present invention, there is provided a semiconductor device comprising a reference circuit for receiving a plurality of impedance control signals and generating a reference voltage, a transmission driving circuit for receiving the impedance control signals and a pair of differential input signals and outputting a pair of differential output signals to an external cable, and an impedance control signal generating circuit for receiving a difference signal of the differential output signals and the reference voltage and generating the impedance control signals.
Preferably, the reference circuit comprises a PMOS transistor with a gate electrode to which a bias voltage is applied and a drain from which the reference voltage is output, a current source connected between a power supply voltage and a source electrode of the PMOS transistor for supplying a current, and a variable impedance circuit connected between the drain electrode of the PMOS transistor and a ground voltage for receiving the impedance control signals and changing resistance value therein.
Preferably, the transmission driving circuit may comprise a first PMOS transistor with a gate electrode to which a first differential input signal is applied and a drain electrode from which a first differential output signal is output, a current source connected between a power supply voltage and a source electrode of the PMOS transistor for supplying a current, a second PMOS transistor with a source electrode connected to the source electrode of the first PMOS transistor, a gate electrode to which a second differential input signal is applied and a drain electrode from which a second differential output signal is output, a first variable impedance circuit connected between the drain electrode of the first PMOS transistor and a ground voltage for receiving the impedance control signals and changing resistance values, and a second variable impedance circuit connected between the drain electrode of the second PMOS transistor and a ground voltage for receiving the impedance control signals and changing resistance values, wherein the first variable impedance circuit and the second variable impedance circuit have the same impedance value at the same time.
Preferably, the variable impedance circuit comprises a plurality of resistors having respective one ends connected commonly to the drain electrode of the first PMOS transistor, and a plurality of NMOS transistors connected between the other end of each of the resistors and a ground voltage, respectively, and having respective gate electrodes to which the respective impedance control signals are applied.
Preferably, the resistors have respective different resistance values ranging from R to 2(Nxe2x88x921)R, when the impedance control signals are consisted of N bits and a resistor having the least resistance value is R. Preferably, the impedance control signal generating circuit comprises a comparator for receiving a difference signal of the first and second differential output signals and the reference voltage, comparing the same with each other, and generating the result signal of the comparison, and a counter for receiving the result signal output from the comparator and generating the impedance control signals.